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cplds designed for migratio n quantum38k? isr? cpld fami ly use delta39k? for all new designs cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-03043 rev. *g revised april 18, 2003 features high density ? 30k to 100k usable gates ? 512 to 1536 macrocells ? 136 to 302 maximum i/o pins ? eight dedicated inputs including four clock pins and four global i/o control signal pins; four jtag inter- face pins for reconfigurability/boundary scan embedded memory ? 16-kb to 48-kb embedded dual-port channel memo- ry 125-mhz in-system operation anyvolt? interface ? 3.3v and 2.5v v cc operation ? 3.3v, 2.5v and 1.8v i/o capability low-power operation ? 0.18-mm 6-layer metal sram-based logic process ? full-cmos implementation of product term array simple timing model ? no penalty for using full 16 product terms/macrocell ? no delay for single product term steering or sharing flexible clocking ? four synchronous clocks per device ? locally generated product term clock ? clock polarity control at each register carry-chain logic for fast and efficient arithmetic opera- tions multiple i/o standards supported ? lvcmos (3.3/3.0/2.5/1.8v), lvttl, 3.3v pci compatible with nobl?, zbt?, and qdr? srams programmable slew rate control on each i/o pin user-programmable bus hold capability on each i/o pin fully 3.3v pci-compliant (as per pci spec rev. 2.2) compact pci hot swap ready multiple package/pinout offering across all densities ? 208 to 484 pins in pqfp and fbga packages ? simplifies design migration across density in-system reprogrammable? (isr?) ? jtag-compliant on-board configuration ? design changes do not cause pinout changes ieee1149.1 jtag boundary scan pin-to-pin-compatible with cypress?s high-end delta39k? cplds allowing easy migration path to ? more embedded memory ? spread aware? pll ? higher density and higher speed devices ? high speed i/o standards and more development software warp ? ? ieee 1076/1164 vhdl or ieee 1364 verilog context sensitive editing ? active-hdl fsm graphical finite state machine editor ? active-hdl sim post-synthesis timing simulator ? architecture explorer for detailed design analysis ? static timing analyzer for critical path analysis ? available on windows 98?, windows nt?, windows me?, windows 2000?, and sun solaris ? 2.5 and later for $99 ? supports all cypress programmable logic products notes: 1. upper limit of typical gates is calculated by assuming that only 50% of the channel memory is used. 2. standby i cc values are with no output load and stable inputs. quantum38k ? isr cpld family members device typical gates [1] macrocells channel memory (kb) maximum i/o pins f max2 (mhz) speed ? t pd pin-to-pin (ns) standby i cc [2] t a =25 c 3.3/2.5v 38k30 16k?48k 512 16 174 125 10 5 ma 38k50 23k?72k 768 24 218 125 10 5 ma 38k100 46k?144k 1536 48 302 125 10 10 ma
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 2 of 45 quantum38k speed bins [3] device 125 83 38k30 x x 38k50 x x 38k100 x x device package offering and i/o count including dedicated clock and control inputs device 208-eqfp 28x28 mm 0.5-mm pitch 256-fbga 17x17 mm 1.0-mm pitch 484-fbga 23x23 mm 1.0-mm pitch 38k30 136 174 38k50 136 180 218 38k100 136 180 302 note: 3. speed bins shown here are for commercial operating ranges. please refer to the quantum38k part numbers (ordering information) on page 24 for industri- al-range speed bins.
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 3 of 45 figure 1. quantum38k100 block diagram (3 rows x 4 columns) with i/o bank structure 4 gclk[3:0] 4 4 4 channel ram 4 gclk[3:0] 4 4 4 4 gclk[3:0] 4 4 4 4 4 gclk[3:0] gctl[3:0] i/o bank 6 i/o bank 7 i/o bank 3 i/o bank 2 i/o bank 4 i/o bank 5 i/o bank 1 i/o bank 0 lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim lb 4 lb 3 lb 0 lb 5 lb 6 lb 7 lb 2 lb 1 pim
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 4 of 45 general description the quantum38k family, based on a 0.18-mm, six-layer metal cmos logic process, offers a wide range of solutions at very high system performance. with devices ranging from 512 to 1536 macrocells, quantum38k is the highest density cpld in the market besides cypress?s delta39k. specifically designed to address high-volume communication applications, this family also integrates cypress?s dual-port memory technology onto a cpld. the architecture is based on logic block clusters (lbc) that are connected by horizontal and vertical (h&v) routing channels. each lbc features eight individual logic blocks (lb). adjacent to each lbc is a channel memory block, which can be accessed directly from the i/o pins. these channel memory blocks are highly configurable and can be cascaded in width and depth. see figure 1 for a block diagram of the quantum38k architecture. all the members of the quantum38k family have cypress?s highly regarded in-system reprogrammability (isr) feature, which simplifies both design and manufacturing flows, thereby reducing costs. the isr feature provides the ability to recon- figure the devices without having design changes cause pinout or timing changes in most cases. the cypress isr function is implemented through a jtag-compliant serial interface. data is shifted in and out through the tdi and tdo pins respectively. superior routability, simple timing, and the isr allows users to change existing logic designs while simul- taneously fixing pinout assignments and maintaining system performance. the entire family features jtag for isr and boundary scan, and is compatible with the pci local bus specification, meeting the electrical and timing requirements. the quantum38k family also features user programmable bus-hold and slew rate control capabilities on each i/o pin. anyvolt interface all quantum38k devices feature an on-chip regulator, which accepts 3.3v or 2.5v on the v cc supply pins and steps it down to 1.8v internally, the voltage level at which the core operates. with quantum38k?s anyvolt technology, the i/o pins can be connected to either 1.8v 2.5v, or 3.3v. all quantum38k devices are 3.3v tolerant regardless of v ccio or v cc settings. global routing description the routing architecture of the quantum38k is made up of h&v routing channels. these routing channels allow signals from each of the quantum38k architectural components to communicate with one another. in addition to the horizontal and vertical routing channels that interconnect the i/o banks, channel memory blocks, and logic block clusters, each lbc contains a programmable interconnect matrix (pim?), which is used to route signals among the logic blocks. figure 2 is a block diagram of the routing channels that interface within the quantum38k architecture. the lbc is exactly the same for every member of the quantum38k cpld family. logic block cluster (lbc) the quantum38k architecture consists of several logic block clusters, each of which have eight logic blocks (lb) connected via a pim, as shown in figure 3 . all lbcs interface with each other via horizontal and vertical routing channels. device v cc v ccio 38k 3.3v or 2.5v 3.3v or 2.5v or 1.8v figure 2. quantum38k routing interface lb cluster pim cluster memory block lb lb lb lb cluster memory block lb lb lb channel memory block i/o block i/o block channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels h-to-v pim v-to-h pim pin inputs from the i/o cells drive dedicated tracks in the horizontal and vertical routing channels 72 72 64 64 lb lb lb lb lb lb lb lb
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 5 of 45 logic block (lb) the logic block is the basic building block of the quantum38k architecture. it consists of a product term array, an intelligent product-term allocator, and 16 macrocells. product term array each logic block features a 72 x 83 programmable product term array. this array accepts 36 inputs from the pim. these inputs originate from device pins and macrocell feedbacks as well as channel memory feedbacks. active low and active high versions of each of these inputs are generated to create the full 72-input field. the 83 product terms in the array can be created from any of the 72 inputs. of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. two of the remaining three product terms in the logic block are used as asynchronous set and asynchronous reset product terms. the final product term is the product term clock (ptclk) and is shared by all 16 macrocells within a logic block. product term allocator through the product term allocator, warp software automati- cally distributes the 80 product terms as needed among the 16 macrocells in the logic block. the product term allocator provides two important capabilities without affecting perfor- mance: product term steering and product term sharing. product term steering product term steering is the process of assigning product terms to macrocells as needed. for example, if one macrocell requires ten product terms while another needs just three, the product term allocator will ?steer? ten product terms to one macrocell and three to the other. on quantum38k devices, product terms are steered on an individual basis. any number between 1 and 16 product terms can be steered to any macrocell. product term sharing product term sharing is the process of using the same product term among multiple macrocells. for example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only programmed once. the quantum38k product term allocator allows sharing across groups of four macrocells in a variable fashion. the software automatically takes advantage of this capability so that the user does not have to intervene. note that neither product term sharing nor product term steering have any effect on the speed of the product. all steering and sharing configurations have been incorporated in the timing specifications for the quantum38k devices. macrocell within each logic block there are 16 macrocells. each macrocell accepts a sum of up to 16 product terms from the product term array. the sum of these 16 product terms can be output in either registered or combinatorial mode. figure 4 displays the block diagram of the macrocell. the register can be asynchronously preset or asynchronously reset at the macrocell level with the separate preset and reset product terms. each of these product terms features programmable polarity. this allows the registers to be preset or reset based on an and expression or an or expression. an xor gate in the quantum38k macrocell allows for many different types of equations to be realized. it can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the d flip-flop into a t flip-flop. the carry-chain input mux allows additional flexibility for the implementation of different types of logic. the macrocell can utilize the carry chain logic to figure 3. quantum38k logic block cluster diagram logic block 0 logic block 1 logic block 3 logic block 2 cluster memory 0 pim logic block 7 logic block 6 logic block 4 logic block 5 cluster memory 1 64 inputs from horizontal routing 64 inputs from vertical routing channel clock inputs gclk[3:0] cc cc cc cc cc cc cc = carry chai n 16 36 16 36 16 36 16 36 16 36 16 36 16 36 8 25 8 25 4 16 36 64 inputs from horizontal routing channel 144 outputs to horizontal and vertical cluster-to-channel pims 64 inputs from vertical routing channel 16
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 6 of 45 implement adders, subtractors, magnitude comparators, parity tree, or even generic xor logic. the output of the macrocell is either registered or combinatorial. carry chain logic the quantum38k macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic operations. the carry logic connects macrocells in up to four logic blocks for a total of 64 macrocells. effective data path operations are implemented through the use of carry-in arith- metic, which drives through the circuit quickly. figure 4 shows that the carry chain logic within the macrocell consists of two product terms (cpt0 and cpt1) from the pta and an input carry-in for carry logic. the inputs to the carry chain mux are connected directly to the product terms in the pta. the output of the carry chain mux generates the carry-out for the next macrocell in the logic block as well as the local carry input that is connected to an input of the xor input mux. carry-in and a configuration bit are inputs to an and gate. this and gate provides a method of segmenting the carry chain in any macrocell in the logic block. macrocell clocks clocking of the register is highly flexible. four global synchronous clocks (gclk[3:0]) and a product term clock (ptclk) are available at each macrocell register. furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell diagram in figure 4 ). preset/reset configurations the macrocell register can be asynchronously preset and reset using the preset and reset mux. both signals are active high and can be controlled by either of two preset/reset product terms (prc[1:0] in figure 4 ) or gnd. in situations where the preset and reset are active at the same time, reset takes priority over preset. figure 4. quantum38k macrocell d q pset res gclk[3:0] ptclk from ptm cpt0 cpt1 prc[1:0] 0 1 0 1 to pim c carry out (to macrocell n+1) carry in (from macrocell n-1) up to 16 pts preset mux clock polarity mux reset mux clock mux carry chain mux xor input mux output mux q c 3 3 2 3 c c c c c c
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 7 of 45 embedded memory the quantum38k architecture includes an embedded channel memory block at each crossing point of horizontal and vertical routing channels. the channel memory is a 4096-bit memory block that can be configured as asynchronous or synchronous single-port ram, dual-port ram, or read-only memory (rom). the memory organization is configurable as 4kx1, 2kx2, 1kx4, or 512x8. data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. all data logic outputs drive dedicated tracks in the horizontal and vertical routing channels. the clocks for the channel memory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. the clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. dual-port (channel memory) configuration each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. the inputs to the dual-port memory are driven from the horizontal and vertical routing channels. the data outputs drive dedicated tracks in the routing channels. the interface to the routing is such that port a of the dual-port interfaces primarily with the horizontal routing channel and port b interfaces primarily with the vertical routing channel. . the clocks for each port of the dual-port configuration are selected from four global clocks and two local clocks. one local clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs of the dual-port memory can also be registered. clocks for the output registers are also selected from four global clocks and two local clocks. one clock polarity mux per port allows the use of true or complement polarity for input and output clocking purposes. arbitration the dual-port configuration of the channel memory block provides arbitration when both ports access the same address at the same time. depending on the memory operations being attempted, one port always gets priority. see table 1 for details on which port gets priority for read and write operations. an active-low ?address match? signal is generated when an address collision occurs. channel memory initialization the channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. to facil- itate the use of look-up-table (lut) logic and rom applica- tions, the channel memory blocks can be initialized with a given set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory routing interface similar to lbc outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in figure 5 . this allows the channel memory blocks to be expanded easily. these dedicated lines can be routed to i/o pins as chip outputs or to other logic block clusters to be used in logic equations. table 1. arbitration result: address match signal becomes active port a port b result of arbitration comment read read no arbitration required both ports read at the same time write read port a gets priority if port b requests first then it will read the current data. the output will then change to the newly written data by port a read write port b gets priority if port a requests first then it will read the current data. the output will then change to the newly written data by port b write write port a gets priority port b is blocked until port a is finished writing
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 8 of 45 i/o banks the quantum38k interfaces the horizontal and vertical routing channels to the pins through i/o banks. there are eight i/o banks per device as shown in figure 6 , and all i/os from an i/o bank are located in the same section of a package for pcb layout convenience. quantum38k devices support true vertical migration?, i.e., for each package type, quantum38k devices of different densities keep given pins in the same i/o banks. this allows for easy and simple implementation of multiple i/o standards during the design and prototyping phase, before a final density has been determined. each i/o bank contains several i/o cells, and each i/o cell contains an input/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. each i/o cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. each i/o bank can use any supported i/o standard by supplying appropriate v ccio voltages. all the v ccio pins in an i/o bank must be connected to the same v ccio voltage. this requirement restricts the number of i/o standards supported by an i/o bank at any given time. the number of i/os which can be used in each i/o bank depend on the type of i/o standards and the number of v ccio and gnd pins being used. this restriction is derived from the electromigration limit of the v ccio and gnd bussing on the chip. please refer to the note on page 14 and the application note titled ?delta39k family device i/o standards and config- urations? for details. i/o cell figure 7 is a block diagram of the quantum38k i/o cell. the i/o cell contains a three-state input buffer, an output buffer, and a register that can be configured as an input or output register. the output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. the input of the device and the pin output can each be configured as registered or combinatorial; however, only one path can be configured as registered in a given design. the output enable can be selected from one of the four global i/o control signals or from one of two output control channel (occ) signals. the output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. the selection is done via a mux that includes v cc and gnd as inputs. i/o signals there are four dedicated inputs (gctl[3:0]) that are used as global i/o control signals available to every i/o cell. these global i/o control signals may be used as output enables, register resets and register clock enables as shown in figure 7 . these global control signals, driven from four dedicated pins, can only be used as active-high signals and are available only to the i/o cells thereby implementing fast resets, register and output enables. figure 5. block diagram of channel memory block 4096-bit dual port array configurable as async/sync dual port configurable as 4kx1, 2kx2, 1kx4 and 512x8 block sizes horizontal channel all channel memory inputs are driven from the routing channels all channel memory outputs drive dedicated tracks in the routing channels gclk[3:0] global clock signals vertical channel delta39k bank 0 bank 1 bank 4 bank 5 bank 2 bank 3 bank 6 bank 7 quantum38k figure 6. quantum38k i/o bank block diagram
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 9 of 45 in addition, there are six output control channel (occ) signals available to each i/o cell. these control signals may be used as output enables, register resets and register clock enables as shown in figure 7 . unlike global control signals, these occ signal can be driven from internal logic or and i/o pin. one of the four global clocks can be selected as the clock for the i/o cell register. the clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock. slew rate control the ouput buffer has a slew rate control option. this allows the output buffer to slew at a fast rate (3 v/ns) or a slow rate (1 v/ns). all i/os default to fast slew rate. for designs concerned with meeting fcc emissions standards the slow edge provides for lower system noise. for designs requiring very high performance the fast edge rate provides maximum system performance. programmable bus hold on each i/o pin, user-programmable-bus-hold is included. bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device?s performance. as a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus-interface applications. bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connec- tions to v cc or gnd. for more information, see the application note ?understanding bus-hold?a feature of cypress cplds?. clocks quantum38k has four dedicated clock input pins (gclk[3:0]) to accept system clocks. the global clock tree for a quantum38k device is driven by the dedicated clock pins, consisting of four global clocks that go to every macrocell, memory block, and i/o cell. clock tree distribution the clock tree distributes the four global clocks to every cluster, channel memory, and i/o block on the die. the global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay. compactpci hot swap compactpci hot swap specification allows the removal and insertion of cards into compactpci sockets without switching-off the bus. quantum38k cplds can be used as a compactpci host or target on these cards. this feature is useful in telecommunication and networking applications as it allows implementation of high availability systems, where repairs and upgrades can be done without downtime. quantum38k cplds are compactpci hot swap ready per compactpci hot swap specification r1.0, with the following exception: io standards i/o standard v ccio lvttl (2 ma ? 24 ma) 3.3v lvcmos 3.3v lvcmos3 3.0v lvcmos2 2.5v lvcmos18 1.8v 3.3v pci 3.3v figure 7. block diagram of i/o cell dq res e global i/o control signals output control channel occ global clock signals slew rate control c i/o from output pim to routing channel oe mux register input mux register enable mux output mux clock mux clock polarity mux register reset mux input mux bus hold c dq res c registered oe mux c c c 3 c 3 c 2 3 c c c
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 10 of 45 the i/o cells do not provide bias voltage support. external resistors can be used to achieve this per section 3.1.3.1 of the compactpci hot swap specification r2.0. a simple board-level solution is provided in the application note titled ?hot-swapping delta39k and quantum38k cplds.? family, package, and density migration in quantum38k cplds the quantum38k cplds combine dense logic with embedded communications memory. further design flexibility is added by the easy migration options available between different packages, densities and even between quantum38k and delta39k cpld families. by making each package offering of quantum38k cpld pin-to-pin compatible with packages of delta39k cpld, a seamless migration path is offered to the users of quantum38k cplds as their design needs grow. delta39k cplds offer following enhancements: ? more embedded memory ? spread aware pll ? high-speed i/os (gtl+, sstl+, hstl etc.) ? higher density devices (up to 200k or 3072 macrocells) ? higher speed devices (up to 233 mhz) ? dedicated fifos with built-in flag logic ? 1.8v operation ? self-boot (one chip) solution eliminates need of a boot eeprom. for details on delta39k cpld family refer to the data sheet titled delta39k isr cpld family . this migration flexibility makes changes or additions to designs simple even after pcb layout. it also provides the ability for experimental designs to be used on production pcbs. please refer to the application note titled ?family, package, and density migration in delta39k and quantum38k cplds? . timing model one important feature of the quantum38k family is the simplicity of its timing. all combinatorial and regis- tered/synchronous delays are worst case and system perfor- mance is static (as shown in the ac specs section) as long as data is routed through the same horizontal and vertical channels. figure 8 illustrates the true timing model for the 38k100 devices. for synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate logic blocks within the same cluster, as well as separate logic blocks within different clusters. this is respec- tively shown as t scs and t scs2 in figure 8. for combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst-case delay in the 38k100 regardless of the amount of logic or which horizontal and vertical channels are used. this is the t pd shown in figure 8. for synchronous systems, the input set-up time to the output macrocell register and the clock to output time are shown as the parameters t mcs and t mcco shown in the figure 8. these measurements are for any output and synchronous clock, regardless of the logic placement. the quantum38k features: no dedicated vs. i/o pin delays no penalty for using 0?16 product terms no added delay for steering product terms no added delay for sharing product terms no output bypass delays. the simple timing model of the quantum38k family eliminates unexpected performance penalties. ieee 1149.1-compliant jtag operation the quantum38k family has an ieee 1149.1 jtag interface for both boundary scan and isr operations. four dedicated pins are reserved on each device for use by the test access port (tap). boundary scan the quantum38k family supports bypass, sample/preload, extest, intest, idcode and usercode boundary scan instruc- tions. the jtag interface is shown in figure 9 . in-system reprogramming (isr) in-system reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. this combination means design changes during debug or field upgrades do not cause board respins. the quantum38k family implements isr by providing a ieee std 1149.1 jtag compliant interface for on-board configu- ration. robust routing resources offer pinout flexibility and a simple timing model provides consistent system performance. configuration quantum38k is a sram based volatile device family that uses cypress?s cy3lv series of cpld boot eeprom to store configuration data. please refer to the data sheet titled ?cpld boot eeprom? and the application note titled ?configuring delta39k/quantum38k? for more details on configuration and interface set-up between quantum38k and cpld boot prom. these documents can be found at http://www.cypress.com. for quantum38k design, configuration is defined as the loading of a user?s design into the volatile quantum38k die. programming, on the other hand, is the loading of a user?s design into the serial boot prom. device configuration can begin in two ways. it can be initiated by toggling the reconfig pin from low to high, or by issuing the appropriate ieee std 1149.1 jtag instruction to the quantum38k device via the jtag interface. there are two ieee std 1149.1 jtag instructions that initiate configuration of the quantum38k. the self config instruction causes the quantum38k to (re)configure with data stored in the serial boot prom. the load config instruction causes the quantum38k to (re)configure according to data provided by other sources such as a pc, automatic test equipment (ate), or an embedded micro-controller/processor via the jtag interface. there are two configuration options available for issuing the ieee std 1149.1 jtag instructions to the quantum38k. the first method is to use a pc with the c3 isr programming cable and software. with this method, the isr pins of the quantum38k devices in the system are routed to a connector at the edge of the printed circuit board. the c3 isr
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 11 of 45 programming cable is then connected between the pc and this connector. a simple configuration file instructs the isr software of the programming operations to be performed on the quantum38k devices in the system. the isr software then automatically completes all of the necessary data manip- ulations required to accomplish configuration, reading, verifying, and other isr functions. for more information on the cypress isr interface, see the isr programming kit data sheet (cy3900i). the second configuration option for the quantum38k is to utilize the embedded controller or processor that already exists in the system. the quantum38k isr software assists in this method by converting the device hex file into the isr serial stream that contains the isr instruction information and the addresses and data of locations to be configured. the embedded controller then simply directs this isr stream to the chain of quantum38k devices to complete the desired recon- figuration or diagnostic operations. contact your local sales office for information on availability of this option. programming there are multiple methods available for programming the serial boot prom. the first method uses cypress?s cydh2200e cpld boot prom programming kit to program via a two-wire interface. the second method is through third-party programmers. programming support for cy3lv series of boot proms is available on a wide variety of third-party programmers. all major programmers (including bp micro, data i/o, system general, hi-lo) support boot prom programming. figure 8. timing model for 38k100 device lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim channel ram 4 gclk[3:0] lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 channel ram 4 channel ram 4 channel ram 4 channel ram 4 gclk[3:0] 4 4 channel ram 4 channel ram 4 gclk[3:0] channel ram 4 channel ram 4 channel ram 4 channel ram channel ram t mcs t pd t scs t mcco t scs2 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim lb 0 lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 pim
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 12 of 45 development software support warp warp is a state-of-the-art design environment for designing with cypress programmable logic. warp utilizes a subset of ieee 1076/1164 vhdl and ieee 1364 as the hardware description language (hdl) for design entry. warp accepts vhdl or verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired quantum38k device. for simulation, warp provides a graphical waveform simulator as well as vhdl and verilog timing models. vhdl and verilog are open, powerful, non-proprietary hardware description languages (hdls) that are standards for behavioral design entry and simulation. hdl allows designers to learn a single language that is useful for all facets of the design process. figure 9. jtag interface instruction register boundary scan idcode usercode isr prog. bypass reg. data registers jtag tap controller tdo tdi tms tclk
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 13 of 45 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .................................. ?65 c to +150 c soldering temperature................................................. 220 c ambient temperature with power applied............................................... ?40 c to +85 c junction temperature .................................................. 135 c v cc to ground potential ...................................?0.5v to 4.6v v ccio to ground potential ................................?0.5v to 4.6v dc voltage applied to outputs in high-z state ?0.5v to 4.5v dc input voltage...............................................?0.5v to 4.5v dc current into outputs ............................................ 20 ma static discharge voltage (per jedec eia/jesd22-a114a) ............................ > 2001v latch-up current..................................................... > 200 ma notes: 4. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 5. input leakage current is 10 a for all the pins on all the quantum38k package except the following pins in quantum 38k100 packages: the input leakage current spec for these pins in 200 a. 6. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. tested initially and after any design or process changes that may affect this par ameter. operating range [4] range ambient temperature junction temperature output condition v ccio v cc v ccjtag / v cccnfg commercial 0 c to +70 c 0 c to +85 c 3.3v 3.3v 0.3v 3.3v 0.3v or 2.5v 0.2v same as v ccio 2.5v 2.5v 0.2v 1.8v 1.8 0.15v industrial ?40 c to +85 c ?40 c to +100 c 3.3v 3.3v 0.3v 2.5v 2.5v 0.2v 1.8v 1.8 0.15v dc characteristics parameter description test conditions v ccio = 3.3v v ccio = 2.5v v ccio = 1.8v unit min. max. min. max. min. max. v drint data retention v cc voltage (config data may be lost below this) 1.5 1.5 1.5 v v drio data retention v ccio voltage (config data may be lost below this) 1.2 1.2 1.2 v i ix [5] input leakage current gnd v i 3.6v ?10 10 ?10 10 ?10 10 a i oz output leakage current gnd v o v ccio ?10 10 ?10 10 ?10 10 a i os [6] output short circuit current v ccio = max., v out = 0.5v ?160 ?160 ?160 a i bhl input bus hold low sustaining current v cc = min., v pin = v il +40 +30 +25 a i bhh input bus hold high sustaining current v cc = min., v pin = v ih ?40 ?30 ?25 a i bhlo input bus hold low overdrive current v cc = max. +250 +200 +150 a i bhho input bus hold high overdrive current v cc = max. ?250 ?200 ?150 a parameter description device v cc = 3.3 v/2.5v unit min. max i cc0 standby current 38k30 20 ma 38k50 20 ma 38k100 30 ma quantum 38k100 package pins 484-fbga b8, g9
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 14 of 45 power-up sequence requirements upon power-up, all the outputs remain three-stated until all the v cc pins have powered-up to the nominal voltage and the part has completed configuration. the part will not start configuration until v cc , v ccio , v ccjtag , and v cccnfg have reached nominal voltage. v cc pins can be powered up in any order. this includes v cc , v ccio , v ccjtag , and v cccnfg . all v ccio s on a bank should be tied to the same potential and powered up together. all v ccio s (even the unused banks) need to be powered up to at least 1.5v before configuration has completed. maximum ramp time for all v cc s should be 0v to nominal voltage in 100 ms. notes: 7. pci spec (rev 2.2) requires the idsel pin to have capacitance less than or equal to 8 pf. section titled ?pin tables? on page 27 identifies all the i/o pins, in a given package, which can be used as idsel in a pci design. all other i/o pins meet the pci requirement of capacitance less than or equal to 10 pf. 8. the number of i/os that can be used in each i/o bank depends on the type of i/o standards and the number of v ccio and gnd pins being used. please refer to the application note titled ?delta39k and quantum38k i/o standards and configurations? for details. the source current limit per i/o bank per v ccio pin is 165 ma. the sink current limit per i/o bank per gnd pin is 230 ma. capacitance parameter description test conditions min. max. unit c i/o input/output capacitance v in =v ccio @ f = 1 mhz 25c 10 pf c clk clock signal capacitance v in =v ccio @ f = 1 mhz 25c 5 12 pf c pci pci-compliant [7] capacitance v in =v ccio @ f = 1 mhz 25c 8 pf dc characteristics [8] (io) input/output standard v ccio (v) v oh (v) v ol (v) v ih (v) v il (v) @ i oh =v oh (min.) @ i ol = v ol (max.) min. max. min. max. lvttl ? 2 ma 3.3 ?2 ma 2.4 2 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvttl ? 4 ma 3.3 ?4 ma 2.4 4 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvttl ? 6 ma 3.3 ?6 ma 2.4 6 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvttl ? 8 ma 3.3 ?8 ma 2.4 8 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvttl ? 12 ma 3.3 ?12 ma 2.4 12 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvttl ? 16 ma 3.3 ?16 ma 2.4 16 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvttl ? 24 ma 3.3 ?24 ma 2.4 24 ma 0.4 2.0 v v ccio +0.3 ?0.3v 0.8v lvcmos 3.3 ?0.1 ma v ccio ?0.2v 0.1 ma 0.2 2.0 v v ccio +0.3 ?0.3v 0.8v lvcmos3 3.0 ?0.1 ma v ccio ?0.2v 0.1ma 0.2 2.0 v v ccio +0.3 ?0.3v 0.8v lvcmos2 2.5 ?0.1 ma 2.1 0.1 ma 0.2 1.7 v v ccio +0.3 ?0.3v 0.7v ?1.0 ma 2.0 1.0 ma 0.4 ?2.0 ma 1.7 2.0 ma 0.7 lvcmos18 1.8 ?0.1 ma v ccio ?0.2v 0.1 ma 0.2 0.65v ccio v ccio +0.3 ?0.3v 0.35v ccio ?2 ma v ccio ?0.45v 2.0 ma 0.45 3.3v pci 3.3 ?0.5 ma 0.9v ccio 1.5 ma 0.1v ccio 0.5v ccio v ccio +0.5 ?0.5v 0.3v ccio configuration parameters parameter description min. unit t reconfig reconfig pin low time before it goes high 200 ns
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 15 of 45 switching characteristics?parameter descriptions over the operating range [9] parameter description combinatorial mode parameters t pd delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster t ea global control to output enable t er global control to output disable t prr asynchronous macrocell reset or preset recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in t pro asynchronous macrocell reset or preset from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels t prw asynchronous macrocell reset or preset minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with synchronous clocking parameters t mcs set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock t mch hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock t mcco global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in t ios set-up time of any input pin to the i/o cell register associated with that pin, relative to a global clock t ioh hold time of any input pin to the i/o cell register associated with that pin, relative to a global clock t ioco clock to output of an i/o cell register to the output pin associated with that register t scs macrocell clock to macrocell clock through array logic within the same cluster t scs2 macrocell clock to macrocell clock through array logic in different clusters on the same channel t ics i/o register clock to any macrocell clock in a cluster on the channel the i/o register is associated with t ocs macrocell clock to any i/o register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in t chz clock to output disable (high-impedance) t clz clock to output enable (low-impedance) f max maximum frequency with internal feedback?within the same cluster f max2 maximum frequency with internal feedback?within different clusters at the opposite ends of a horizontal or vertical channel product term clock t mcspt set-up time for macrocell used as input register, from input to product term clock t mchpt hold time of macrocell used as an input register t mccopt product term clock to output delay from input pin t scs2pt register to register delay through array logic in different clusters on the same channel using a product term clock channel interconnect parameters t chsw adder for a signal to switch from a horizontal to vertical channel and vice-versa t cl2cl cluster to cluster delay adder (through channels and channel pim) miscellaneous delays t cpld delay from the input of a cluster pim, through a macrocell in the cluster, back to a cluster pim input. this parameter can be added to the t pd and t scs parameters for each extra pass through the and/or array required by a given signal path t mccd adder for carry chain logic per macrocell t iod delay from the input of the output buffer to the i/o pin note: 9. add t chsw to signals making a horizontal to ve rtical channel switch or vice-versa.
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 16 of 45 t ioin delay from the i/o pin to the input of the channel buffer t ckin delay from the clock pin to the input of the clock driver t ioregpin delay from the i/o pin to the input of the i/o register jtag parameters t jckh tclk high time t jckl tclk low time t jcp tclk clock period t jsu jtag port set-up time (tdi/tms inputs) t jh jtag port hold time (tdi/tms inputs) t jco jtag port clock to output time (tdo) t jxz jtag port valid output to high impedance (tdo) t jzx jtag port high impedance to valid output (tdo) switching characteristics?parameter descriptions over the operating range [9] (continued) parameter description channel memory timing parameter descriptions over the operating range parameter description dual port asynchronous mode parameters t chmaa channel memory access time. delay from address change to read data out t chmpwe write enable pulse width t chmsa address set-up to the beginning of write enable t chmha address hold after the end of write enable with both signals from the same i/o block t chmsd data set-up to the end of write enable t chmhd data hold after the end of write enable t chmba channel memory asynchronous dual port address match (busy access time) dual-port synchronous mode parameters t chmcyc1 clock cycle time for flow through read and write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) t chmcyc2 clock cycle time for pipelined read and write operations (from channel memory input register through the memory to channel memory output register) t chms address, data, and we set-up time of pin inputs, relative to a global clock t chmh address, data, and we hold time of pin inputs, relative to a global clock t chmdv1 global clock to data valid on output pins for flow through data t chmdv2 global clock to data valid on output pins for pipelined data t chmbdv channel memory synchronous dual-port address match (busy, clock to data valid) t chmmacs1 channel memory input clock to macrocell clock in the same cluster t chmmacs2 channel memory output clock to macrocell clock in the same cluster t macchms1 macrocell clock to channel memory input clock in the same cluster t macchms2 macrocell clock to channel memory output clock in the same cluster internal parameters t chmchaa asynchronous channel memory access time from input of channel memory to output of channel memory
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 17 of 45 switching characteristics?parameter values over the operating range parameter 125 83 unit min. max. min. max. combinatorial mode parameters t pd 10 15 ns t ea 9 10 ns t er 9 10 ns t prr 8.0 10 ns t pro 13 15 ns t prw 6.0 7.0 ns synchronous clocking parameters t mcs 5.0 6.7 ns t mch 0.0 0.0 ns t mcco 10 12 ns t ios 2.0 2.5 ns t ioh 2.0 2.5 ns t ioco 7.0 8.0 ns t scs 6.4 9.6 ns t scs2 8.0 12 ns t ics 8.0 12 ns t ocs 8.0 12 ns t chz 6.0 7.0 ns t clz 1.5 1.5 ns f max 156 104 mhz f max2 125 83 mhz product term clocking parameters t mcspt 5.0 6.0 ns t mchpt 2.0 2.5 ns t mccopt 11.0 15.0 ns t scs2pt 10.0 15.0 ns channel interconnect parameters t chsw 1.7 2.0 ns t cl2cl 2.8 3.0 ns miscellaneous parameters t cpld 4.0 5.0 ns t mccd 0.35 0.38 ns jtag parameters t jckh 25 25 ns t jckl 25 25 ns t jcp 50 50 ns t jsu 10 10 ns t jh 10 10 ns t jco 20 20 ns t jxz 20 20 ns t jzx 20 20 ns
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 18 of 45 input and output standard timing delay adjustments all the timing specifications in this data sheet are specified based on lvcmos-compliant inputs and outputs (fast slew rates [10] ). apply the following adjustments if the inputs and outputs are configured to operate at the following standards. input/output standard output delay adjustments input delay adjustments fast slew rate slow slew rate (additional delay to fast slew rate) t iod t ea t er t iodslow t easlow t erslow t ioin t ckin t ioregpin lvttl ? 2 ma 2.75 0 0 2.6 2.0 2.0 0 0 0 lvttl ? 4 ma 1.8 0 0 2.5 2.0 2.0 0 0 0 lvttl ? 6 ma 1.8 0 0 2.5 2.0 2.0 0 0 0 lvttl ? 8 ma 1.2 0 0 2.4 2.0 2.0 0 0 0 lvttl ? 12 ma 0.6 0 0 2.3 2.0 2.0 0 0 0 lvttl ? 16 ma 0.16 0 0 2.0 2.0 2.0 0 0 0 lvttl ? 24 ma 0.0 0 0 1.6 2.0 2.0 0 0 0 lvcmos 0.00 02.02.02.00 0 0 lvcmos3 0.14 0.05 0 2.0 2.0 2.0 0.1 0.1 0.2 lvcmos2 0.41 0.1 0 2.0 2.0 2.0 0.2 0.2 0.4 lvcmos18 1.6 0.7 0.1 2.1 2.0 2.0 0.5 0.4 0.3 3.3v pci ?0.14 0 0 2.0 2.0 2.0 0 0 0 channel memory timing parameter values parameter 125 83 unit min. max. min. max. dual-port asynchronous mode parameters t chmaa 17 20 ns t chmpwe 10 12 ns t chmsa 3.2 4.0 ns t chmha 1.8 2.0 ns t chmsd 10 12 ns t chmhd 0.9 1.0 ns t chmba 14.0 16.0 ns dual-port synchronous mode parameters t chmcyc1 15 20 ns t chmcyc2 7.4 10.6 ns t chms 5.0 6.0 ns t chmh 0.0 0.0 ns t chmdv1 17 20 ns t chmdv2 10 15 ns t chmbdv 14.0 16.0 ns t chmmacs1 14.0 16.0 ns t chmmacs2 8.0 10 ns t macchms1 7.6 9.0 ns t macchms2 10.0 13.0 ns internal parameters t chmchaa 10.0 13.0 ns note: 10. for ?slow slew rate? output delay adjustments, refer to warp software?s static timing analyzer results.
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 19 of 45 switching waveforms t pd input combinatorial output combinatorial output registered output with synchronous clocking (macrocell) t mcs input synchronous t mcco registered output t mch clock registered input in i/o cell t ios data input input register clock t ioco registered output t ioh clock to clock input register clock macrocell register clock t scs t ics pt clock to pt clock data pt clock t scs2pt t mcspt input
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 20 of 45 switching waveforms (continued) asynchronous reset/preset input t pro registered output clock t prr t prw reset/preset output enable/disable global control t er outputs t ea input channel memory dp asynchronous timing write t chmpwe t chmsa t chmha t chmaa t chmhd address data output t chmaa a n?1 a n a n+1 a n+2 d n d n-1 d n d n+1 t chmsd enable input
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 21 of 45 switching waveforms (continued) channel memory internal clocking clock input clock output clock t chmmacs1 t macchms2 t chmmacs2 t macchms1 macrocell input channel memory channel memory channel memory dp sram flow through r/w timing clock t chmcyc1 t chmh t chms write d n+1 t chms t chmh output a n+1 a n+2 a n+3 a n address t chmdv1 t chmdv1 t chmdv1 d n?1 d n+3 d n?1 a n?1 data t chmdv1 d n+3 d n+2 d n+1 d n enable input
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 22 of 45 switching waveforms (continued) channel memory dp sram pipeline r/w timing a n+1 a n+2 d n+1 t chmcyc3 t chmh t chms t chms t chmh a n t chms t chmh a n+3 a n?1 d n+3 d n?1 d n?1 t chmdv2 t chmdv2 d n d n+1 d n+2 t chmdv2 clock write output address data enable input dual-port asynchronous address match busy signal address a a n a n?1 a n a n+1 address t chmba t chmba b n address b match
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 23 of 45 switching waveforms (continued) clock a n a n b n?1 b n+1 t chmbdv a n?1 t chmbdv t chms t chms address b address dual-port synchronous address match busy signal address a match p in count 2 08 = 208 leads 2 56 = 256 balls 4 84 = 484 balls c y 3 8 1 0 0 v 4 8 4 - 125 b b c c ypress semiconductor id f amily type 3 8 = quantum38k family g ate density 30=30k usable gates 50=50k usable gates 100=100k usable gates speed 125 = 125 mhz 83 = 83 mhz package type n = plastic quad flat pack (pqfp) nt = thermally enhanced quad flat pack (eqf p bb = fine-pitch ball grid array (fbga) 1.0-mm lead pitch operating conditions commercial 0c to +70c industrial -40c to +85c o perating reference voltage v = 3.3v or 2.5v supply voltage
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 24 of 45 quantum38k part numbers (ordering information) device speed (mhz) ordering code package name package type operating range 38k30 125 CY38030V208-125NC n208 208-lead plastic quad flat pack commercial cy38030v256-125bbc bb256 256-lead fine pitch ball grid array cy38030v208-125ni n208 208-lead plastic quad flat pack industrial cy38030v256-125bbi bb256 256-lead fine pitch ball grid array 83 cy38030v208-83nc n208 208-lead plastic quad flat pack commercial cy38030v256-83bbc bb256 256-lead fine pitch ball grid array 38k50 125 cy38050v208-125nc n208 208-lead plastic quad flat pack commercial cy38050v256-125bbc bb256 256-lead fine pitch ball grid array cy38050v484-125bbc bb484 484-lead fine pitch ball grid array cy38050v208-125ni n208 208-lead plastic quad flat pack industrial cy38050v256-125bbi bb256 256-lead fine pitch ball grid array cy38050v484-125bbi bb484 484-lead fine pitch ball grid array 83 cy38050v208-83nc n208 208-lead plastic quad flat pack commercial cy38050v256-83bbc bb256 256-lead fine pitch ball grid array cy38050v484-83bbc bb484 484-lead fine pitch ball grid array 38k100 125 cy38100v208-125ntc nt208 208-lead enhanced quad flat pack commercial cy38100v256-125bbc bb256 256-lead fine pitch ball grid array cy38100v484-125bbc bb484 484-lead fine pitch ball grid array cy38100v208-125nti nt208 208-lead enhanced quad flat pack industrial cy38100v256-125bbi bb256 256-lead fine pitch ball grid array cy38100v484-125bbi bb484 484-lead fine pitch ball grid array 83 cy38100v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy38100v256-83bbc bb256 256-lead fine pitch ball grid array cy38100v484-83bbc bb484 484-lead fine pitch ball grid array cpld boot eeprom [11] part numbers (ordering information) cpld boot eeprom density speed (mhz) ordering code package name package type operating range 1 mbit 15 cy3lv010-10jc 20j 20-lead plastic leaded chip carrier commercial 10 cy3lv010-10ji 20j 20-lead plastic leaded chip carrier industrial 512kbit 15 cy3lv512-10jc 20j 20-lead plastic leaded chip carrier commercial 10 cy3lv512-10ji 20j 20-lead plastic leaded chip carrier industrial recommended cpld boot eeprom for corresponding quantum38k cplds cpld device recommended cpld boot eeprom cypress atmel 38k30 cy3lv512 at17lv512 38k50 cy3lv512 at17lv512 38k100 cy3lv010 at17lv010
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 25 of 45 package diagrams note: 11. see the data sheet titled ?cy3lv512/010 512k/1-mbit cpld boot eeprom? for detailed architectural and timing information. 51-85069-*b 208-lead plastic quad flatpack (pqfp) n208 208-lead enhanced quad flatpack (eqfp) nt208
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 26 of 45 package diagrams (continued) 256-ball fbga (17 x 17 mm) bb256 51-85108-*c 20-lead plastic leaded chip carrier j61 51-85000-*a
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 27 of 45 pin tables the following table identifies the bank assignments for the global clock and control signals for the quantum38k devices. the bank assignments are the same for all densities and all packages. table 2. pin definition table pin name function pin description cclk output configuration clock for serial interface with the external boot prom config_done output flag indicating that configuration is complete data input pin to receive configuration data from the external boot prom gclk0-3 input global clock signals 0 through 3 cce output chip select for the external boot prom (active low) gctl0-3 input global control signals 0 through 3 gnd ground ground io0 input/output i/o for bank 0 io1 input/output i/o for bank 1 io2 input/output i/o for bank 2 io3 input/output i/o for bank 3 io4 input/output i/o for bank 4 io5 input/output i/o for bank 5 io6 input/output i/o for bank 6 io7 input/output i/o for bank 7 reconfig input pin to start configuration of quantum38k reset output reset signal to interface with the external boot prom tclk input jtag test clock tdi input jtag test data in tdo output jtag test data out tms input jtag test mode select v cc power operating voltage v ccio0 power v cc for i/o bank 0 v ccio1 power v cc for i/o bank 1 v ccio2 power v cc for i/o bank 2 v ccio3 power v cc for i/o bank 3 v ccio4 power v cc for i/o bank 4 v ccio5 power v cc for i/o bank 5 v ccio6 power v cc for i/o bank 6 v ccio7 power v cc for i/o bank 7 v ccjtag power v cc for jtag pins v cccnfg power v cc for configuration port
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 28 of 45 table 3. global signal bank assignments data sheet pin name bank number gclk0 0 gclk1 5 gclk2 6 gclk3 7 gctl0 0 gctl1 5 gctl2 6 gctl3 7 table 4. 208 eqfp pin table pin cy38030 cy38050 cy38100 1 gctl0 gctl0 gctl0 2 gnd gnd gnd 3 gclk0 gclk0 gclk0 4 gnd gnd gnd 5 io0 io0 io0 6 io0 io0 io0 7 io0 io0 io0 8 io0 io0 io0 9 io0 io0 io0 10 io0 io0 io0 11 v ccio0 v ccio0 v ccio0 12 io0 io0 io0 13 io0 io0 io0 14 io0 io0 io0 15 io0 io0 io0 16 io0 io0 io0 17 io0 io0 io0 18 io0 io0 io0 19 io0 io0 io0 20 v ccio0 v ccio0 v ccio0 21 [12] io0 io0 io0 22 [12] io0 io0 io0 23 v cc v cc v cc 24 gnd gnd gnd 25 nc nc v cc 26 nc nc gnd 27 [12] io0 io0 io0 28 v ccio0 v ccio0 v ccio0 29 v ccio1 v ccio1 v ccio1 30 [12] io1 io1 io1 31 [12] io1 io1 io1 32 [12] io1 io1 io1 note: 12. capacitance on these i/o pins meets the pci spec (rev. 2.2), which requires idsel pin in a pci design to have capacitance le ss than or equal to 8 pf. in the document titled ?quantum38k cpld family data sheet?, this spec is defined as c pci. all other i/o pins have a capacitance less than or equal to 10 pf.
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 29 of 45 33 io1 io1 io1 34 io1 io1 io1 35 v ccio1 v ccio1 v ccio1 36 gnd gnd gnd 37 io1 io1 io1 38 io1 io1 io1 39 io1 io1 io1 40 io1 io1 io1 41 io1 io1 io1 42 io1 io1 io1 43 io1 io1 io1 44 io1 io1 io1 45 v cc v cc v cc 46 v ccio1 v ccio1 v ccio1 47 gnd gnd gnd 48 io1 io1 io1 49 io1 io1 io1 50 io1 io1 io1 51 io1 io1 io1 52 v cccnfg v cccnfg v cccnfg 53 data data data 54 config_done config_done config_done 55 reset reset reset 56 reconfig reconfig reconfig 57 cce cce cce 58 cclk cclk cclk 59 v cccnfg v cccnfg v cccnfg 60 v cccnfg v cccnfg v cccnfg 61 io2 io2 io2 62 io2 io2 io2 63 io2 io2 io2 64 io2 io2 io2 65 io2 io2 io2 66 v ccio2 v ccio2 v ccio2 67 gnd gnd gnd 68 io2 io2 io2 69 io2 io2 io2 70 io2 io2 io2 71 io2 io2 io2 72 io2 io2 io2 73 gnd gnd gnd 74 v ccio2 v ccio2 v ccio2 75 v cc v cc v cc 76 gnd gnd gnd 77 nc nc v cc table 4. 208 eqfp pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 30 of 45 78 nc nc gnd 79 io2 io2 io2 80 io2 io2 io2 81 [12] io2 io2 io2 82 [12] io2 io2 io2 83 [12] io2 io2 io2 84 v ccio2 v ccio2 v ccio2 85 v ccio3 v ccio3 v ccio3 86 [12] io3 io3 io3 87 [12] io3 io3 io3 88 [12] io3 io3 io3 89 v ccio3 v ccio3 v ccio3 90 gnd gnd gnd 91 io3 io3 io3 92 io3 io3 io3 93 io3 io3 io3 94 io3 io3 io3 95 io3 io3 io3 96 io3 io3 io3 97 io3 io3 io3 98 v ccio3 v ccio3 v ccio3 99 io3 io3 io3 100 gnd gnd gnd 101 io3 io3 io3 102 io3 io3 io3 103 io3 io3 io3 104 io3 io3 io3 105 io4 io4 io4 106 io4 io4 io4 107 io4 io4 io4 108 io4 io4 io4 109 io4 io4 io4 110 io4 io4 io4 111 v ccio4 v ccio4 v ccio4 112 gnd gnd gnd 113 io4 io4 io4 114 v cc v cc v cc 115 io4 io4 io4 116 io4 io4 io4 117 io4 io4 io4 118 io4 io4 io4 119 io4 io4 io4 120 io4 io4 io4 121 io4 io4 io4 122 [12] io4 io4 io4 table 4. 208 eqfp pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 31 of 45 123 [12] io4 io4 io4 124 v ccio4 v ccio4 v ccio4 125 gnd gnd gnd 126 [12] io4 io4 io4 127 v cc v cc v cc 128 gnd gnd gnd 129 nc nc v cc 130 nc nc gnd 131 v ccio4 v ccio4 v ccio4 132 v ccio5 v ccio5 v ccio5 133 [12] io5 io5 io5 134 [12] io5 io5 io5 135 [12] io5 io5 io5 136 io5 io5 io5 137 io5 io5 io5 138 v ccio5 v ccio5 v ccio5 139 io5 io5 io5 140 io5 io5 io5 141 io5 io5 io5 142 io5 io5 io5 143 io5 io5 io5 144 io5 io5 io5 145 io5 io5 io5 146 io5 io5 io5 147 io5 io5 io5 148 v ccio5 v ccio5 v ccio5 149 io5 io5 io5 150 io5 io5 io5 151 io5 io5 io5 152 gnd gnd gnd 153 gclk1 gclk1 gclk1 154 gnd gnd gnd 155 gctl1 gctl1 gctl1 156 tdo tdo tdo 157 tclk tclk tclk 158 tdi tdi tdi 159 v ccjtag v ccjtag v ccjtag 160 gclk2 gclk2 gclk2 161 gnd gnd gnd 162 tms tms tms 163 gctl2 gctl2 gctl2 164 io6 io6 io6 165 io6 io6 io6 166 io6 io6 io6 167 io6 io6 io6 table 4. 208 eqfp pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 32 of 45 168 io6 io6 io6 169 v ccio6 v ccio6 v ccio6 170 io6 io6 io6 171 io6 io6 io6 172 io6 io6 io6 173 io6 io6 io6 174 io6 io6 io6 175 io6 io6 io6 176 io6 io6 io6 177 gnd gnd gnd 178 v ccio6 v ccio6 v ccio6 179 v cc v cc v cc 180 gnd gnd gnd 181 v cc v cc v cc 182 gnd gnd gnd 183 [12] io6 io6 io6 184 [12] io6 io6 io6 185 [12] io6 io6 io6 186 v ccio6 v ccio6 v ccio6 187 v ccio7 v ccio7 v ccio7 188 [12] io7 io7 io7 189 [12] io7 io7 io7 190 [12] io7 io7 io7 191 v ccio7 v ccio7 v ccio7 192 io7 io7 io7 193 io7 io7 io7 194 io7 io7 io7 195 io7 io7 io7 196 io7 io7 io7 197 io7 io7 io7 198 io7 io7 io7 199 v ccio7 v ccio7 v ccio7 200 io7 io7 io7 201 io7 io7 io7 202 io7 io7 io7 203 io7 io7 io7 204 io7 io7 io7 205 gnd gnd gnd 206 gclk3 gclk3 gclk3 207 gnd gnd gnd 208 gctl3 gctl3 gctl3 table 4. 208 eqfp pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 33 of 45 table 5. 256 fbga pin table pin cy38030 cy38050 cy38100 a1 gnd gnd gnd a2 io7 io7 io7 a3 io7 io7 io7 a4 io7 io7 io7 a5 io7 io7 io7 a6 io7 io7 io7 a7 nc io7 io7 a8 io6 io6 io6 a9 io6 io6 io6 a10 io6 io6 io6 a11 io6 io6 io6 a12 io6 io6 io6 a13 io6 io6 io6 a14 io6 io6 io6 a15 io6 io6 io6 a16 gnd gnd gnd b1 io0 io0 io0 b2 gnd gnd gnd b3 io7 io7 io7 b4 io7 io7 io7 b5 io7 io7 io7 b6 v ccio7 v ccio7 v ccio7 b7 vcc v cc v cc b8 io7 io7 io7 b9 nc io6 io6 b10 v cc v cc v cc b11 v ccio6 v ccio6 v ccio6 b12 io6 io6 io6 b13 io6 io6 io6 b14 io6 io6 io6 b15 gnd gnd gnd b16 tdo tdo tdo c1 io0 io0 io0 c2 io0 io0 io0 c3 gnd gnd gnd c4 io7 io7 io7 c5 io7 io7 io7 c6 v ccio7 v ccio7 v ccio7 c7 v ccio7 v ccio7 v ccio7 c8 [12] nc io7 io7 c9 [12] io6 io6 io6 c10 v ccio6 v ccio6 v ccio6 c11 v ccio6 v ccio6 v ccio6 c12 io6 io6 io6
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 34 of 45 c13 io6 io6 io6 c14 gnd gnd gnd c15 tdi tdi tdi c16 io5 io5 io5 d1 io0 io0 io0 d2 io0 io0 io0 d3 io0 io0 io0 d4 gnd gnd gnd d5 io7 io7 io7 d6 io7 io7 io7 d7 io7 io7 io7 d8 [12] io7 io7 io7 d9 [12] nc io6 io6 d10 io6 io6 io6 d11 io6 io6 io6 d12 io6 io6 io6 d13 gnd gnd gnd d14 tclk tclk tclk d15 io5 io5 io5 d16 io5 io5 io5 e1 io0 io0 io0 e2 io0 io0 io0 e3 io0 io0 io0 e4 io0 io0 io0 e5 io7 io7 io7 e6 io7 io7 io7 e7 io7 io7 io7 e8 [12] io7 io7 io7 e9 [12] io6 io6 io6 e10 io6 io6 io6 e11 io6 io6 io6 e12 tms tms tms e13 io5 io5 io5 e14 io5 io5 io5 e15 io5 io5 io5 e16 io5 io5 io5 f1 io0 io0 io0 f2 v cc v cc v cc f3 v ccio0 v ccio0 v ccio0 f4 io0 io0 io0 f5 io0 io0 io0 f6 io7 io7 io7 f7 gctl3 gctl3 gctl3 f8 gclk3 gclk3 gclk3 table 5. 256 fbga pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 35 of 45 f9 gctl2 gctl2 gctl2 f10 gclk2 gclk2 gclk2 f11 io5 io5 io5 f12 io5 io5 io5 f13 io5 io5 io5 f14 v ccio5 v ccio5 v ccio5 f15 v ccjtag v ccjtag v ccjtag f16 io5 io5 io5 g1 io0 io0 io0 g2 nc nc v cc g3 v ccio0 v ccio0 v ccio0 g4 io0 io0 io0 g5 io0 io0 io0 g6 gctl0 gctl0 gctl0 g7 gnd gnd gnd g8 gnd gnd gnd g9 gnd gnd gnd g10 gnd gnd gnd g11 gctl1 gctl1 gctl1 g12 io5 io5 io5 g13 io5 io5 io5 g14 v ccio5 v ccio5 v ccio5 g15 nc nc vcc g16 io5 io5 io5 h1 [12] io0 io0 io0 h2 [12] io0 io0 io0 h3 [12] io0 io0 io0 h4 io0 io0 io0 h5 io0 io0 io0 h6 gclk0 gclk0 gclk0 h7 gnd gnd gnd h8 gnd gnd gnd h9 gnd gnd gnd h10 gnd gnd gnd h11 gclk1 gclk1 gclk1 h12 io5 io5 io5 h13 io5 io5 io5 h14 [12] io5 io5 io5 h15 [12] io5 io5 io5 h16 [12] io5 io5 io5 j1 io1 io1 io1 j2 io1 io1 io1 j3 [12] io1 io1 io1 j4 [12] io1 io1 io1 table 5. 256 fbga pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 36 of 45 j5 [12] io1 io1 io1 j6 io1 io1 io1 j7 gnd gnd gnd j8 gnd gnd gnd j9 gnd gnd gnd j10 gnd gnd gnd j11 io4 io4 io4 j12 [12] io4 io4 io4 j13 [12] io4 io4 io4 j14 [12] io4 io4 io4 j15 io5 io5 io5 j16 io5 io5 io5 k1 io1 io1 io1 k2 v cc v cc v cc k3 v ccio1 v ccio1 v ccio1 k4 io1 io1 io1 k5 io1 io1 io1 k6 io1 io1 io1 k7 gnd gnd gnd k8 gnd gnd gnd k9 gnd gnd gnd k10 gnd gnd gnd k11 io4 io4 io4 k12 io4 io4 io4 k13 io4 io4 io4 k14 v ccio4 v ccio4 v ccio4 k15 v cc v cc v cc k16 io4 io4 io4 l1 io1 io1 io1 l2 nc nc v cc l3 v ccio1 v ccio1 v ccio1 l4 io1 io1 io1 l5 v cccnfg v cccnfg v cccnfg l6 config_done config_done config_done l7 io2 io2 io2 l8 [12] io2 io2 io2 l9 [12] io3 io3 io3 l10 io3 io3 io3 l11 io3 io3 io3 l12 io4 io4 io4 l13 io4 io4 io4 l14 v ccio4 v ccio4 v ccio4 l15 v cc v cc v cc l16 io4 io4 io4 table 5. 256 fbga pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 37 of 45 m1 io1 io1 io1 m2 io1 io1 io1 m3 io1 io1 io1 m4 data data data m5 reconfig reconfig reconfig m6 io2 io2 io2 m7 io2 io2 io2 m8 [12] io2 io2 io2 m9 [12] io3 io3 io3 m10 io3 io3 io3 m11 io3 io3 io3 m12 io3 io3 io3 m13 io4 io4 io4 m14 io4 io4 io4 m15 io4 io4 io4 m16 io4 io4 io4 n1 io1 io1 io1 n2 io1 io1 io1 n3 io1 io1 io1 n4 gnd gnd gnd n5 v cccnfg v cccnfg v cccnfg n6 io2 io2 io2 n7 io2 io2 io2 n8 [12] io2 io2 io2 n9 [12] io3 io3 io3 n10 io3 io3 io3 n11 io3 io3 io3 n12 io3 io3 io3 n13 gnd gnd gnd n14 io4 io4 io4 n15 io4 io4 io4 n16 io4 io4 io4 p1 io1 io1 io1 p2 io1 io1 io1 p3 gnd gnd gnd p4 cce cce cce p5 io2 io2 io2 p6 v ccio2 v ccio2 v ccio2 p7 v ccio2 v ccio2 v ccio2 p8 io2 io2 io2 p9 io2 io2 io2 p10 v ccio3 v ccio3 v ccio3 p11 v ccio3 v ccio3 v ccio3 p12 io3 io3 io3 table 5. 256 fbga pin table (continued) pin cy38030 cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 38 of 45 p13 io3 io3 io3 p14 gnd gnd gnd p15 io4 io4 io4 p16 io4 io4 io4 r1 io1 io1 io1 r2 gnd gnd gnd r3 cclk cclk cclk r4 io2 io2 io2 r5 io2 io2 io2 r6 v cccnfg v cccnfg v cccnfg r7 v ccio2 v ccio2 v ccio2 r8 io2 io2 io2 r9 io2 io2 io2 r10 v cc v cc v cc r11 v ccio3 v ccio3 v ccio3 r12 io3 io3 io3 r13 io3 io3 io3 r14 io3 io3 io3 r15 gnd gnd gnd r16 io4 io4 io4 t1 gnd gnd gnd t2 reset reset reset t3 io2 io2 io2 t4 io2 io2 io2 t5 io2 io2 io2 t6 io2 io2 io2 t7 nc io2 io2 t8 io2 io2 io2 t9 io2 io2 io2 t10 nc io3 io3 t11 io3 io3 io3 t12 io3 io3 io3 t13 io3 io3 io3 t14 io3 io3 io3 t15 io3 io3 io3 t16 gnd gnd gnd table 5. 256 fbga pin table (continued) pin cy38030 cy38050 cy38100 table 6. 484 fbga pin table pin cy38050 cy38100 a1 gnd gnd a2 gnd gnd a3 nc nc a4 nc nc a5 io7 io7 a6 io7 io7 a7 nc io7 a8 io7 io7 a9 io7 io7 a10 io7 io7 table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 39 of 45 a11 gnd gnd a12 gnd gnd a13 io6 io6 a14 io6 io6 a15 io6 io6 a16 nc io6 a17 io6 io6 a18 io6 io6 a19 nc nc a20 nc nc a21 gnd gnd a22 gnd gnd b1 gnd gnd b2 gnd gnd b3 nc nc b4 v ccio7 v ccio7 b5 nc io7 b6 io7 io7 b7 nc io7 b8 io7 io7 b9 nc nc b10 io7 io7 b11 io7 io7 b12 io6 io6 b13 io6 io6 b14 nc nc b15 io6 io6 b16 nc io6 b17 io6 io6 b18 io6 io6 b19 v ccio6 v ccio6 b20 nc nc b21 gnd gnd b22 gnd gnd c1 nc nc c2 nc nc c3 nc nc c4 nc io7 c5 nc io7 c6 io7 io7 c7 nc io7 c8 io7 io7 c9 io7 io7 c10 io7 io7 table 6. 484 fbga pin table (continued) pin cy38050 cy38100 c11 io7 io7 c12 io6 io6 c13 nc io6 c14 io6 io6 c15 io6 io6 c16 nc io6 c17 io6 io6 c18 io6 io6 c19 io6 io6 c20 nc nc c21 nc nc c22 nc nc d1 nc nc d2 v ccio0 v ccio0 d3 nc nc d4 gnd gnd d5 nc io7 d6 nc io7 d7 io7 io7 d8 io7 io7 d9 io7 io7 d10 nc io7 d11 io6 io6 d12 io6 io6 d13 io6 io6 d14 io6 io6 d15 io6 io6 d16 nc io6 d17 nc io6 d18 io6 io6 d19 gnd gnd d20 nc nc d21 v ccio5 v ccio5 d22 nc nc e1 nc nc e2 nc nc e3 nc nc e4 io0 io0 e5 gnd gnd e6 io7 io7 e7 io7 io7 e8 io7 io7 e9 v ccio7 v ccio7 e10 v cc v cc table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 40 of 45 e11 io7 io7 e12 nc io6 e13 v cc v cc e14 v ccio6 v ccio6 e15 nc io6 e16 nc io6 e17 nc io6 e18 gnd gnd e19 tdo tdo e20 nc nc e21 nc nc e22 nc nc f1 nc nc f2 nc io0 f3 io0 io0 f4 io0 io0 f5 io0 io0 f6 gnd gnd f7 io7 io7 f8 io7 io7 f9 v ccio7 v ccio7 f10 v ccio7 v ccio7 f11 [12] io7 io7 f12 [12] io6 io6 f13 v ccio6 v ccio6 f14 v ccio6 v ccio6 f15 io6 io6 f16 nc io6 f17 gnd gnd f18 tdi tdi f19 io5 io5 f20 io5 io5 f21 nc io5 f22 nc nc g1 nc nc g2 io0 io0 g3 nc io0 g4 io0 io0 g5 io0 io0 g6 io0 io0 g7 gnd gnd g8 io7 io7 g9 nc io7 g10 io7 io7 table 6. 484 fbga pin table (continued) pin cy38050 cy38100 g11 [12] io7 io7 g12 [12] io6 io6 g13 io6 io6 g14 io6 io6 g15 io6 io6 g16 gnd gnd g17 tclk tclk g18 io5 io5 g19 io5 io5 g20 io5 io5 g21 io5 io5 g22 nc nc h1 nc nc h2 io0 io0 h3 io0 io0 h4 io0 io0 h5 nc io0 h6 nc io0 h7 nc io0 h8 io7 io7 h9 io7 io7 h10 io7 io7 h11 [12] io7 io7 h12 [12] io6 io6 h13 io6 io6 h14 io6 io6 h15 tms tms h16 io5 io5 h17 io5 io5 h18 io5 io5 h19 io5 io5 h20 io5 io5 h21 io5 io5 h22 nc nc j1 nc nc j2 nc nc j3 nc io0 j4 nc io0 j5 nc v cc j6 v ccio0 v ccio0 j7 io0 io0 j8 nc io0 j9 io7 io7 j10 gctl3 gctl3 table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 41 of 45 j11 gclk3 gclk3 j12 gctl2 gctl2 j13 gclk2 gclk2 j14 io5 io5 j15 io5 io5 j16 io5 io5 j17 v ccio5 v ccio5 j18 v ccjtag v ccjtag j19 nc io5 j20 nc io5 j21 nc nc j22 nc nc k1 nc nc k2 io0 io0 k3 nc io0 k4 io0 io0 k5 v cc v cc k6 v ccio0 v ccio0 k7 io0 io0 k8 nc io0 k9 gctl0 gctl0 k10 gnd gnd k11 gnd gnd k12 gnd gnd k13 gnd gnd k14 gctl1 gctl1 k15 nc io5 k16 io5 io5 k17 v ccio5 v ccio5 k18 nc v cc k19 nc io5 k20 nc io5 k21 nc io5 k22 nc nc l1 gnd gnd l2 io0 io0 l3 io0 io0 l4 [12] io0 io0 l5 [12] io0 io0 l6 [12] io0 io0 l7 io0 io0 l8 nc io0 l9 gclk0 gclk0 l10 gnd gnd table 6. 484 fbga pin table (continued) pin cy38050 cy38100 l11 gnd gnd l12 gnd gnd l13 gnd gnd l14 gclk1 gclk1 l15 nc io5 l16 io5 io5 l17 [12] io5 io5 l18 [12] io5 io5 l19 [12] io5 io5 l20 io5 io5 l21 nc io5 l22 gnd gnd m1 gnd gnd m2 nc io1 m3 io1 io1 m4 io1 io1 m5 nc io1 m6 [12] io1 io1 m7 [12] io1 io1 m8 [12] io1 io1 m9 io1 io1 m10 gnd gnd m11 gnd gnd m12 gnd gnd m13 gnd gnd m14 io4 io4 m15 [12] io4 io4 m16 [12] io4 io4 m17 [12] io4 io4 m18 nc io5 m19 nc io5 m20 io4 io4 m21 io4 io4 m22 gnd gnd n1 nc nc n2 nc io1 n3 nc io1 n4 nc io1 n5 v cc v cc n6 v ccio1 v ccio1 n7 io1 io1 n8 nc io1 n9 nc io1 n10 gnd gnd table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 42 of 45 n11 gnd gnd n12 gnd gnd n13 gnd gnd n14 nc io4 n15 io4 io4 n16 io4 io4 n17 v ccio4 v ccio4 n18 v cc v cc n19 nc io4 n20 nc io4 n21 nc io4 n22 nc nc p1 nc nc p2 nc nc p3 io1 io1 p4 nc io1 p5 v cc v cc p6 v ccio1 v ccio1 p7 nc io1 p8 v cccnfg v cccnfg p9 config_done config_done p10 io2 io2 p11 [12] io2 io2 p12 [12] io3 io3 p13 io3 io3 p14 io3 io3 p15 nc io4 p16 io4 io4 p17 v ccio4 v ccio4 p18 v cc v cc p19 nc io4 p20 nc io4 p21 nc nc p22 nc nc r1 nc nc r2 nc io1 r3 io1 io1 r4 io1 io1 r5 io1 io1 r6 io1 io1 r7 data data r8 reconfig reconfig r9 io2 io2 r10 io2 io2 table 6. 484 fbga pin table (continued) pin cy38050 cy38100 r11 [12] io2 io2 r12 [12] io3 io3 r13 io3 io3 r14 io3 io3 r15 nc io3 r16 nc io4 r17 nc io4 r18 nc io4 r19 io4 io4 r20 io4 io4 r21 io4 io4 r22 nc nc t1 nc nc t2 io1 io1 t3 io1 io1 t4 io1 io1 t5 io1 io1 t6 io1 io1 t7 gnd gnd t8 v cccnfg v cccnfg t9 io2 io2 t10 io2 io2 t11 [12] io2 io2 t12 [12] io3 io3 t13 io3 io3 t14 io3 io3 t15 io3 io3 t16 gnd gnd t17 io4 io4 t18 io4 io4 t19 io4 io4 t20 io4 io4 t21 io4 io4 t22 nc nc u1 nc nc u2 io1 io1 u3 io1 io1 u4 io1 io1 u5 io1 io1 u6 gnd gnd u7 cce cce u8 io2 io2 u9 v ccio2 v ccio2 u10 v ccio2 v ccio2 table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 43 of 45 u11 io2 io2 u12 io2 io2 u13 v ccio3 v ccio3 u14 v ccio3 v ccio3 u15 io3 io3 u16 io3 io3 u17 gnd gnd u18 io4 io4 u19 io4 io4 u20 io4 io4 u21 io4 io4 u22 nc nc v1 nc nc v2 nc nc v3 nc nc v4 nc nc v5 gnd gnd v6 cclk cclk v7 io2 io2 v8 nc io2 v9 v cccnfg v cccnfg v10 v ccio2 v ccio2 v11 io2 io2 v12 io2 io2 v13 nc v cc v14 v ccio3 v ccio3 v15 io3 io3 v16 io3 io3 v17 io3 io3 v18 gnd gnd v19 nc nc v20 nc nc v21 nc nc v22 nc nc w1 nc nc w2 v ccio1 v ccio1 w3 nc nc w4 gnd gnd w5 reset reset w6 io2 io2 w7 nc io2 w8 io2 io2 w9 nc io2 w10 nc io2 table 6. 484 fbga pin table (continued) pin cy38050 cy38100 w11 io2 io2 w12 io2 io2 w13 nc io3 w14 nc io3 w15 io3 io3 w16 io3 io3 w17 io3 io3 w18 nc io3 w19 gnd gnd w20 nc nc w21 v ccio4 v ccio4 w22 nc nc y1 nc nc y2 nc nc y3 nc nc y4 io2 io2 y5 io2 io2 y6 io2 io2 y7 io2 io2 y8 nc io2 y9 nc io2 y10 io2 io2 y11 io2 io2 y12 io3 io3 y13 io3 io3 y14 io3 io3 y15 io3 io3 y16 io3 io3 y17 io3 io3 y18 nc io3 y19 nc io3 y20 nc nc y21 nc nc y22 nc nc aa1 gnd gnd aa2 gnd gnd aa3 nc nc aa4 v ccio2 v ccio2 aa5 io2 io2 aa6 io2 io2 aa7 nc io2 aa8 io2 io2 aa9 nc nc aa10 nc io2 table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 44 of 45 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. warp is a registered trademark, and nobl, pim, spread aware, anyvolt, self-boot, in-system reprogrammable, isr, delta39k, and quantum38k are trademarks, of cypress semiconductor corporation. windows 98, windows 2000, windows nt, and windows me are trademarks of microsoft co rporation. solaris is a trademarks of sun microsystems, inc. zbt is a trademark of idt. qdr is a trademark of micron, idt, and cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. aa11 io2 io2 aa12 io3 io3 aa13 io3 io3 aa14 nc nc aa15 io3 io3 aa16 nc io3 aa17 nc io3 aa18 io3 io3 aa19 v ccio3 v ccio3 aa20 nc nc aa21 gnd gnd aa22 gnd gnd ab1 gnd gnd ab2 gnd gnd ab3 nc nc ab4 nc nc ab5 io2 io2 ab6 io2 io2 ab7 io2 io2 ab8 nc io2 ab9 nc io2 ab10 nc io2 ab11 gnd gnd ab12 gnd gnd ab13 io3 io3 ab14 io3 io3 ab15 io3 io3 ab16 nc io3 ab17 io3 io3 ab18 nc io3 ab19 nc nc ab20 nc nc ab21 gnd gnd ab22 gnd gnd table 6. 484 fbga pin table (continued) pin cy38050 cy38100
quantum38k? isr? cpld fami ly document #: 38-03043 rev. *g page 45 of 45 document history page document title: quantum38k? isr? cplds designed for migration document number: 38-03043 rev. ecn no. issue date orig. of change description of change ** 106747 04/25/01 szv new data sheet convert from spec number 38-01058 to 38-03043 *a 108380 07/19/01 rn deleted 38k15 device from the data sheet. deleted 144fbga package from the data sheet. changed esd spec from ?mil-std-883? to ?jedec eia./jesd22-a114-a?. changed the two bin offerings for all devices from ?83 mhz and 66 mhz? to ?125 mhz and 83 mhz? respectively changed the timing specs accordingly changed the part ordering information accordingly added paragraph about quantum38k being compactpci hot swap ready. updated i/o standard timing delay specs and changed the default i/o standard from 3.3v pci to lvcmos. added standby icc spec *b 109680 09/25/01 rn removed revision ?b? from cy38k100 part number removed errata from cy38k100 devices, as it is no longer applicable 208-pin package will now be ?thermally enhanced quad flat pack? (208-eqfp) instead of plastic quad flat pack (pqfp) for better heat dissi- pation and power management *c 111959 12/21/01 rn combine with spec# 38-04042 *d 112947 04/23/02 rn updated pinouts for quantum38k30 and quantum38k50 packages updated standby current (icc0) spec on page 13 added a section titled ?family, package and density migration in quantum38k cplds? on page 10 added slow slew rate timing delay adjustments to table on page 18 added table 3 on page 28 identifying bank assignments of global control/clock signals *e 117519 09/17/02 oor changed data sheet status from preliminary to final added note #4 to dc characteristics (p.12) *f 122239 12/28/02 rbi power up requirements added to operating range information *g 125910 04/22/03 oor added note to title page: ?use delta39k cpld for all new designs?

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